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By John G. Webster (Editor)

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Automated Synthesis of Clock Distribution Networks Much of the current research focuses on automating the synthesis of clock distribution networks to support higher performance requirements. The optimal placement of localized distributed buffers, improved delay models that account for nonlinear active transistor behavior, the use of localized clock skew to increase circuit speed, and the integration of RC interconnect and buffer physical delay models for more accurate delay analysis must be considered in the automated design and layout of clock distribution networks.

Minimal work exists, however, in developing circuit procedures and algorithms for automating the circuit design of clock distribution networks in structured custom VLSI circuits (64–67). One primary requirement for developing these algorithms is a physical model for estimating the delay of the clock signal path. An important observation is that the accuracy required to calculate delay differences (as in clock skew) is much greater than that required when calculating absolute delay values (as in the delay of a clock path).

Time is ‘‘stolen’’ from adjacent data paths to increase system performance). Therefore, the descriptive term ‘‘cycle stealing’’ is used to describe this process. Dagenais and Rumin (128,129) present a timing analysis system that determines important clocking parameters from a circuit specification of the system, such as the minimum clock period and hold time. This approach is useful for top-down design when performing exploratory estimation of system performance. SPECIFICATION OF THE OPTIMAL TIMING CHARACTERISTICS OF CLOCK DISTRIBUTION NETWORKS An important element in the design of clock distribution networks is choosing the minimum local clock skews that increase circuit performance by reducing the maximum clock period while ensuring that no race conditions exist.

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